Semiconductor devices are subject to many competing design goals. Since it is very often desirable to minimize the size of electronic apparatus, surface mount semiconductor devices are often used due to their small footprint. Solder nodules or “bumps” having spherical, near-spherical, or other shapes are frequently used to join an IC to a substrate, such as a printed circuit board (PCB). The IC and substrate have corresponding metallized locations generally known as contact points, or bond pads. The components are aligned, typically using sophisticated optical aligning tools. Solder bumps positioned at the prepared metallized locations are heated, and solder bonds are formed between the contact points upon cooling. When completed, the IC-to-substrate assembly solder joints are typically “blind,” that is, they are not readily accessible for visual inspection. The soldered IC and substrate are then encapsulated in a protective plastic package in order to complete the IC assembly. Often, underfill material is interposed between the IC and substrate as well, in order to provide increased strength and protection.
Among the problems encountered with packaged IC assemblies, some of the most common and debilitating are the separation of layers, and open or short circuits caused by poor solder connections, or subsequent separation of materials, or the ingress of moisture between separated materials. For these reasons, secure solder bonds and void-free underfill and encapsulant materials are highly desirable. The size of the solder bumps used in the formation of solder bonds is generally determined by area considerations, which often include the need for numerous solder joints in close proximity. Small solder bumps are the result. As a side effect of reduced solder bump size, stand-off height, the vertical distance between IC and substrate, can also be reduced. Stand-off height is commonly limited to solder bump height, or less, due to the partial collapse of the solder during reflow. Reductions in the stand-off height can create problems related to soldering, packaging, and reliability in general. Reduced stand-off height between the die and substrate can result in increased stress among dielectric layers of the IC assembly. A reduction in stand-off height also increases the difficulty of making void-free underfills. These and other problems can lead to reduced reliability in the packaged IC assembly.
Due to these and other problems, improved integrated circuit assemblies with increased stand-off height, and methods for their manufacture, would be useful and advantageous in the arts.